1. Field of the Invention
The present invention relates to a driver circuit for use with an active matrix display and, more particularly, to a redundant shift register circuit configuration and also to a switching method.
2. Description of the Related Art
Shift register circuits using thin-film transistors (TFTs) are employed in image-sensor driver circuits and in liquid crystal display driver circuits. In recent years, such shift register circuits are often used in driver circuits for active matrix displays.
An active matrix display has pixels arranged at intersections in a matrix construction. Every pixel is equipped with a switching device. Image information is controlled by switching on and off each switching device. In the present invention, three-terminal devices, especially thin-film transistors each having a gate electrode, a source electrode, and a drain electrode, are used as switching devices. The display medium in such a display device can be liquid crystal materials, plasma, and other substances whose optical characteristics such as reflectivity, index of refraction, transmittivity, and intensity of emitted light can be varied.
In the present specification, the rows of a matrix construction are signal lines (gate lines) which extend parallel to each other and are connected to the gate electrodes of the transistors of their respective rows. The columns of the matrix construction are signal lines (source lines) which extend parallel to each other and are connected with the source (drain) electrodes of the transistors of their respective columns. A circuit for driving the gate lines is referred to herein as a gate driver circuit. A circuit for driving the source lines is referred to herein as a source driver circuit. Thin-film transistors are referred to herein as TFTs.
In a gate driver circuit, shift registers are arranged in a line and connected in series to generate a vertical scanning timing signal for an active matrix display. The number of the shift registers is equal to the number of the vertically extending gate lines. In this gate driver circuit, the TFTs in the active matrix display are switched on and off.
In a source driver circuit, shift registers are arranged in a line and connected in series to provide a display of the horizontal image data component of image data to be displayed on an active matrix display. The number of the shift registers is equal to the number of the horizontally extending source lines. The analog switches are turned on and off by pulse pulses synchronized with a horizontal scanning signal.
The TFTs are electrically activated inside the active matrix display by the source driver circuit in this way. Thus, the state of each pixel cell (i.e., whether the cell is activated or not) is controlled.
An ordinary active matrix display is now described by referring to FIG. 6. A shift register circuit X generates a timing signal in the vertical direction of the active matrix display so that a video signal is retained in an analog memory. The video signal held in the analog memory is applied to an analog buffer at the timing determined by a latch pulse. The analog buffer supplies a video signal to the source lines for the TFTs inside the active matrix display at the timing determined by the latch pulse.
On the other hand, a shift register circuit Y generates a timing signal in the horizontal direction of the active matrix display. An ON signal is applied to the gate lines for the TFTs on the same scanning line. A video signal supplied to the source lines for the TFTs determines the orientation of the pixel cells connected with the drain electrodes of the TFTs.
Generally, shift register circuits are available in forms as shown in FIGS. 7 and 8. Shift register circuits frequently use D flip-flop circuits. The shift register circuit shown in FIG. 7 utilizes analog switches. The shift register circuit shown in FIG. 8 employs clocked inverters.
In FIG. 7, if the level of the clock pulse CK is high (H), and if the level of an input signal DATA is high (H), a p-type TFT of a complementary transfer gate 701 is biased into conduction. At this time, the input signal DATA is passed through complementary inverter circuits 702 and 703. Under this condition, none of complementary transfer gates 704 and 705 are conducting.
If the level of the clock pulse CK is low (L), and if the level of the input signal DATA is high (H), then the complementary transfer gate 701 does not conduct. The previous output level H is retained. The p-type TFT of the complementary transfer gate 704 conducts. This causes the complementary inverter circuit 702 to bring the level of the input signal DATA to a low level (L).
With respect to the complementary transfer gate 705, if the level at the output terminal of the complementary transfer gate 705 is low (L), then this is same level as the level at the input terminal. In this state, no current flows.
However, output signal Q is made to go high (H) via a complementary inverter circuit 706. If the level at the output terminal of the complementary transfer gate 705 is high (H), then the n-type TFT is driven into conduction. The complementary inverter circuit 702 recovers electric charge, thus inverting the level to a low level (L).
Also at this time, the output signal Q is made to go high (H) via the complementary inverter circuit 706. In either case, the output signal Q is at a high level (H). At this time, the complementary transfer gate 708 does not conduct.
If the level of the clock pulse CK is high (H), and if the level of the input signal DATA is low (L), the n-type TFT of the complementary transfer gate 701 conducts. The input signal DATA is made to go low (L) via the complementary inverter circuits 702 and 703.
At this time, none of the complementary transfer gates 704 and 705 conduct but the previous output level L is retained. The n-type TFT of the complementary transfer gate 708 conducts. A signal of a low level (L) is applied to the complementary inverter circuit 706. The output signal Q is maintained at a high level (H).
If the level of the clock pulse CK is low (L), and if the level of the input signal DATA is low (L), the n-type TFT of the complementary transfer gate 704 conducts as mentioned previously. This causes the complementary inverter circuit 702 to bring the input signal DATA to a high level (H).
At the same time, the p-type TFT of the complementary transfer gate 705 conducts. The output signal Q is made to go low (L) via the complementary inverter circuit 706. At this time, the complementary transfer gate 708 is not conducting. In this way, a D flip-flop circuit is formed by the analog switches.
In FIG. 8, if the level of the clock pulse CK is high (H), and if the level of the input signal DATA is high (H), the level of the output from a complementary clocked inverter circuit 801 is low (L). This level is inverted to a high level (H) via a complementary inverter circuit 802. At this time, none of complementary clocked inverter circuits 803 and 804 are conducting.
If the level of the clock pulse CK is low (L), and if the level of the input data DATA is high (H), the complementary clocked inverter circuit 803 are biased into conduction. The output level is made to go low (L). A signal of a high level (H) is applied to the complementary clocked inverter circuit 804 again via the complementary inverter circuit 802.
The complementary clocked inverter circuit 804 conducts, inverting the output level to a low level (L). This is applied to the complementary inverter circuit 805, which in turn produces a signal of a high level (H). The level of the output signal Q is high (H). At this time, the complementary clocked inverter circuit 806 is not conducting.
If the level of the clock pulse CK is high (H), and if the level of the input signal DATA is low (L), the complementary clocked inverter circuit 801 conducts. The output level is made to go high (H). This level is inverted to a low level (L) via the complementary inverter circuit 802.
At this time, none of the complementary clocked inverter circuits 803 and 804 are conducting. However, the high-level output (H) held by the complementary inverter circuit 805 is applied to the conducting complementary clocked inverter circuit 806. As a result, the output level is made to go low (L). Accordingly, the level of the output signal Q is maintained high (H) via the complementary inverter circuit 805.
If the level of the clock pulse CK is low (L), and if the level of the input signal DATA is low (L), the complementary clocked inverter circuit 803 conducts, causing the output level to go high (H). A signal of a low level (L) is applied to the complementary clocked inverter circuit 804 again via the complementary inverter circuit 802.
The complementary inverter circuit 804 is biased into conduction. The output level is made to go high (H). This is applied to the complementary inverter circuit 805, which in turn produces a low-level signal (L). The output signal Q is made to go low (L). In this state, the complementary clocked inverter circuit 806 is cut off. In this manner, a D flip-flop circuit is built from the clocked inverters.
In the prior art shift register circuits forming the gate and source driver circuits, respectively, of an active matrix display, shift register circuits which are equal in number with the gate lines and source lines of the display device are connected in series as shown in FIGS. 4 and 5, respectively.
In the case of the gate driver circuit, the outputs of the shift register circuits are connected with the gate lines via an inverter type buffer circuit, as shown in FIG. 4.
In the case of the source driver circuit, the outputs of the shift register circuits are connected with the control terminal of a sampling transmission gate via an inverter type buffer circuit, as shown in FIG. 5.
For this reason, if the shift register circuits connected in series contain at least one defective or faulty flip-flop circuit, then image data and the scanning time for the display device which are delivered from the flip-flop circuits connected after the defective flip-flop circuit are not normal. Hence, a precise image cannot be obtained.
It is known that a redundant circuit having a plurality of shift register circuits can be provided to prevent the above-described undesirable situation. Where this configuration is adopted, during fabrication, a waveform showing the pattern obtained from one shift register circuit is observed. If a defect is found, the pattern of the shift register circuit is cut by a laser beam or the like. The operating shift register circuit is switched to the preliminary shift register circuit. Therefore, dedicated tools and installation are necessary. In this construction, if any one shift register circuit becomes defective after the apparatus has been assembled, then the apparatus must be disassembled, and the substrate holding the shift register circuit must be replaced with a new one.